The present invention relates generally to an external power mode control method and circuitry and in particular, to external control of chip power up states.
FIG. 1 shows a block diagram of a conventional approach for controlling chip power up (including wake up) of a chip in a computer platform. Depicted are first and second chips, 102 and 112 respectively, coupled together, among other ways, via power up signals. For example, the first chip could be an I/O hub controller, and the second chip could be a graphics hub controller in a mobile platform system. The power up signals typically include signals such as power good, reset, and low power state indication signals that are appropriately asserted and deasserted to properly start up the second chip.
In operation, chip 1 comes up first, e.g., when the platform power is turned on, and once it is powered up, it then controls chip 2 to come up. (Not all of the chips in a computer platform are shown for simplicity, but others such as a processor chip could also be included.) The power up signals are implemented with separate pins in the first and second chips, which unfortunately, can limit the different things that can be done at power up due to limited pin resources. With such limited power-up functionality, there may be various problems such as reliability issues. For example, with many chips, sometime, while power up is occurring, the second chip may sense one or more of its fuse settings, e.g., for operating conditions or to provide to other chips. Unfortunately, depending on how the fuses are sensed, they can be sensed for too long, resulting in possible degradation over the life of the chip. Accordingly, new approaches may be desired.